Designing high-speed digital circuits in Verilog HDL — Booth encoding, FPGA synthesis, timing closure. M.Tech Microelectronics & VLSI · CGPA 8.44
I'm an RTL Design Engineer specializing in digital hardware design, working at the intersection of algorithm optimization and FPGA implementation. My focus is building circuits that are not just correct — but fast, lean, and timing-clean.
My graduate research at the M.Tech level centred on arithmetic circuit optimization: combining Booth radix-4 encoding with hybrid adder trees to push multiplication performance well beyond ripple-carry baselines on Xilinx Artix-7 silicon.
I validate everything — 1,024 test vectors, zero violations. Design without verification is guesswork.
8×8-bit multiplier combining Booth radix-4 encoding with a Carry-Select / Carry-Lookahead hybrid adder tree. Synthesized and validated on Xilinx Artix-7 (Basys 3).
Full ALU supporting arithmetic and logical operations with 100 MHz performance on Artix-7. Optimized logic paths and comprehensive testbench coverage.
Mealy/Moore hybrid FSM for a 4-way traffic intersection. Implemented in Verilog, synthesized to Basys 3, with full state-transition validation and waveform verification.
Available for full-time positions, internships, and collaborations.